A continuing trend in semiconductor technology is to build integrated circuit chips with more and faster circuits on the chip. The drive toward this ultra large scale integration, has resulted in continued shrinking of features, with the result that a large number of devices are available on a chip. To take advantage of this large number of devices and form them into a large number of circuits, the various devices have to be interconnected. The ability to connect as many devices as possible is called wirability, which is the percentage of the available devices on the chip that can be connected together to form usable circuits.
The term "interconnect" as used herein, refers to any electrically conductive element such as a wire or a strap connecting two parts of the circuits. Depending on the circuits, the length of the interconnects can vary. Short interconnects connect adjacent devices, and longer interconnects connect devices further apart thus forming more complex circuits, and also making connections to Input/Output devices and power supplies. In general, there is a range and distribution of lengths of the interconnect used on a chip. In addition, the interconnects must be electrically insulated from each other except where designed to make contact. Multilevel wiring planes or levels are used, with each wiring level electrically isolated by an insulator from another wiring level. Electrical connection between wires on different planes is made where desired through the use of sloped or vertical holes in the insulator. Hence, the interconnects have both horizontal elements, referred to as "wires", and vertical elements referred to as "studs" or "vias". Studs or vias connect wires in different wiring planes. When a vertical and horizontal interconnect member contact each other, it is important how they intersect each other. Referring to FIG. 1B, the vertical element can be fully overlapped or covered by the horizontal element at the point of intersection. This is called a "bordered contact". Alternatively, as shown in FIG. 1A, the two elements can merely cross each other thereby providing some nominal contact area at the intersection. This is called a "borderless contact".
Wirability is affected by the design constraints that govern whether bordered or borderless contacts are used. These constraints are often imposed by process limitations or reliability needs with respect to the contacts being designed. For a given set of minimum space/wire size, maximum wirability is achieved by use of borderless contacts, as the wires and spaces can be designed to the smallest features and spaces allowed. In contrast, wirability is adversely affected by constraints that require bordered contacts, since larger surface areas are required for the contacts as seen in FIG. 1B. Bordered contacts provide intersection areas larger than the stud cross section areas.
Designers, in laying out the wiring, use the wiring level immediately above the device surface to make the local connections of essentially adjacent devices to form the basic circuits (see for example, "An efficient and flexible architecture for high density gate arrays", by Veendrick, H.J.M et al., IEEE J. Solid State Circuits, Vol. 25, No. 5, pp. 1153-1157). The other wiring levels are then used for connecting the basic circuit blocks to each other to form more complex circuits and ultimately leading to the input/output terminals of the chips for distributing power and information signals to the devices. A local interconnection level can improve wiring efficiency and reduce the number of total wiring levels that would be otherwise required. The electrical resistivity required for this interconnect wiring is dependent on the specific applications, the type of circuit and the transistor device, bipolar or FET. The electrical resistivity specification determines the thickness and the choice of the material for the local interconnect.
A key process difficulty associated with the formation of the local interconnect is the topography of the device surface. The device surface is quite non-planar, and the device contacts, such as the emitter, base and collector are in general at different elevations. In the case of FETs, the gate is at a different elevation than the source and drain. In addition, the device forming processes, such as recessed oxide isolation, shallow trenches and other process steps, create topographical irregularities (hereinafter called steps) between device contacts on the surface. A good local interconnect process, must provide good step coverage and also should be high yielding, producing a minimum number of defects that cause open and short circuits. A lift-off process using sacrificial resist stencils, can be used to fabricate borderless contacts; however lift-off processes tend to be limited to deposition temperatures of less than 200.degree. C., and thus limiting the choice of materials to those that can be directionally deposited. A conductor thus deposited by a lift-off process, tends to have poor (or thinner) step coverage, making the interconnect unreliable or open over steps. A subtractive process is therefore often preferred, wherein a blanket film is deposited by chemical vapor deposition (CVD), sputtering or plasma enhanced CVD techniques. The blanket film is then subtractively etched into a desired pattern by using a resist mask. A major problem in subtractive etching of a conductive film over the aforementioned topography, is the occurrence of residual metal, sometimes called "stringers", that result from the incomplete etching of films at the steps, thereby causing electrical shorts. Extended over-etching is often required to reduce or eliminate these shorts.
It would be particularly valuable in the art, especially as it relates to the local interconnection of devices on a semiconductor substrate, for a method to be provided that would form a conductor having low electrical resistivity, with minimal shorting and good conductor coverage over steps, and furthermore would allow the use of borderless intersections in the design.